//
// This program is free software: you can redistribute it and/or modify
// it under the terms of the GNU Lesser General Public License as published by
// the Free Software Foundation, either version 3 of the License, or
// (at your option) any later version.
// 
// This program is distributed in the hope that it will be useful,
// but WITHOUT ANY WARRANTY; without even the implied warranty of
// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
// GNU Lesser General Public License for more details.
// 
// You should have received a copy of the GNU Lesser General Public License
// along with this program.  If not, see http://www.gnu.org/licenses/.
// 

package mesh_switch.simulations;

//
// TODO auto-generated module
//
simple Outer
{
    parameters:
        // 发送模式，用于设置数据包的空间分布：uniform_random模式、LTR模式
        string send_mode = default("uniform_random");
        // 发送时间间隔，用于设置数据包的时间分布：常数分布、泊松分布 exponential(xxx)
        double send_interval = default(3e-6);
        // 设备的坐标值
        int x;
        int y;
        // 设备的开关
        bool outer_enable = default(false);
        // LTR通信的值
        double ltr_rate = default(0.7);
        // 统计包时延 Latnecy、发送包数量 Send、接收包数量 Recv、发送bit数 SendBit（实际上是byte）、接收bit数 RecvBit（实际上是byte）
        // 统计跳数值 Hop、发送时间 SendTime、接收时间 RecvTime
        @display("i=block/rxtx");
        @signal[latency_reg](type="double");
        @signal[send_reg](type="long");
        @signal[recv_reg](type="long");
        @signal[sendBit_reg](type="long");
        @signal[recvBit_reg](type="long");
        @signal[hop_reg](type="long");
        @signal[sendTime_reg](type="double");
        @signal[recvTime_reg](type="double");
        
        @statistic[Latnecy](title="Latnecy"; source="latency_reg"; record=vector,stats; interpolationmode=none);
        @statistic[Send](title="Send"; source="send_reg"; record=vector,stats; interpolationmode=none);
        @statistic[Recv](title="Recv"; source="recv_reg"; record=vector,stats; interpolationmode=none);
        @statistic[SendBit](title="SendBit"; source="sendBit_reg"; record=vector,stats; interpolationmode=none);
        @statistic[RecvBit](title="RecvBit"; source="recvBit_reg"; record=vector,stats; interpolationmode=none);
        @statistic[Hop](title="Hop"; source="hop_reg"; record=vector,stats; interpolationmode=none);
        @statistic[SendTime](title="SendTime"; source="sendTime_reg"; record=vector,stats; interpolationmode=none);
        @statistic[RecvTime](title="RecvTime"; source="recvTime_reg"; record=vector,stats; interpolationmode=none);
        
    gates:
        inout outer_port;
}
